AMD Memory Hierarchy: Part 3 of HIP Training Series, Sep 18, 2023
HIP® is a parallel computing platform and programming model that extends C++ to allow developers to program GPUs with a familiar programming language and simple APIs.
AMD will present a multi-part HIP training series intended to help new and existing GPU programmers understand the main concepts of the HIP programming model. Each part will include a 1-hour presentation and example exercises. The exercises are meant to reinforce the material from the presentation and can be completed during a 1-hour hands-on session following each lecture.
This training series is open to OLCF and NERSC users via Zoom. OLCF users will be using HIP for AMD GPUs on Frontier. NERSC users will be using HIP for Nvidia GPUs on Perlmutter. Please note that participants will register for each part of the series individually.
Part 3: AMD Memory Hierarchy
Date and Time: 10 a.m. - 12 p.m. (Pacific time), Monday, September 18, 2023
This presentation on the AMD Memory Hierarchy will take a deeper look into the AMD GPU hardware. With an understanding of GPU memory systems and in particular the AMD GPU memory system, we’ll explore how we can improve the performance of applications. This understanding is crucial to designing code to perform well. We’ll look at register usage and how to optimize your application for the best utilization of this precious resource. Then we’ll look at occupancy and what might limit it in your application kernels. We’ll then cover the use of the local data store (LDS) that is available for each workgroup and the use of shuffle instructions for even more performance. The hands-on exercises will have examples of implementing each of these optimizations. While this presentation targets the AMD GPU hardware, many of the same ideas work on other vendor hardware.
Not yet available.