NERSCPowering Scientific Discovery Since 1974

The Software Challenges of Petascale Computing

An Interview with Kathy Yelick

November 10, 2006


Kathy Yelick is a professor of computer science at UC Berkeley. She has a joint appointment in Berkeley Lab's Computational Research Division, where she is the lead for the Division's Future Technologies Group and the Berkeley Institute for Performance Studies. Kathy received her Bachelors, Masters, and PhD degrees in Electrical Engineering and Computer Science from the Massachusetts Institute of Technology. Her research interests include parallel computing, memory hierarchy optimizations, programming languages and compilers.

(Reprinted with permission from the November 10, 2006 issue of HPCwire)

In this HPCwire interview, Kathy Yelick, one of the world's leading performance evaluation experts, discusses software challenges related to petascale and other large-scale computing systems. Yelick is a professor of computer science at UC Berkeley, with a joint appointment in Lawrence Berkeley Lab's Computational Research Division, where she leads the Future Technologies Group and the Berkeley Institute for Performance Studies.

HPCwire: Are petascale initiatives putting enough emphasis on software?

Yelick: No. Unfortunately, the race for each major performance milestone, in this case petascale, has resulted in a de-emphasis on software. Procurement teams and system developers vying for the first petascale platform need to put as much money as possible into hardware in order to be first. This leaves less funding for software. The situation has gotten worse over the past decade, when multiple agencies were supporting HPC software development.

HPCwire: Assuming the important goal isn't peak or Linpack petaflops performance, but sustained petaflops performance across a spectrum of applications, what software challenges need to be addressed?

Yelick: The major software challenge facing the petascale efforts is the explosion in hardware parallelism, which will require a complete redesign of applications, libraries, and algorithms to reach the level of parallelism needed to fully utilize a petascale machine. This parallelism increase is coming from the introduction of multi-core processors within the compute nodes and the trend towards building machines out of a larger number of smaller compute nodes. Other challenges include the hierarchical nature of these machines, the use of hardware accelerators such as SIMD units within compute nodes, and the trend toward lower degree networks. Full crossbars for petascale machines are unaffordable. Software needs to adapt to these features, and I believe it will. The question is how general the solutions will be and therefore how large the set of petascale applications will be. The reliability of these systems is also a major concern, and one that I think represents the largest risk for specific machines. We need to have better methods for handling hardware and software failures throughout the software stack.

HPCwire: Which of these software challenges are hardest? How much can be accomplished by the 2010 timeframe?

Yelick: Reliability is probably the hardest, because so far we have written user-level software assuming that the lower level system is mostly reliable. Checkpointing is the only commonly used technique, and the Berkeley Lab Checkpoint/Restart project is developing software for petascale systems; but this model is useful only as long as failures are not too frequent. There are research efforts to develop new ways of writing fault-tolerant software, but the solution is not yet clear. In the meantime, we need to do a very good job of testing systems software, in particular operating systems, to reduce the frequency of failures.

HPCwire: With compilers, there is the challenge of scaling to petaflop architectures and also the challenge of handling heterogeneous architectures with multiple processor types that a number of vendors are talking about. Can you comment on these challenges?

Yelick: Heterogeneous processors represent a new compiler challenge, because, at the very least, they increase the optimization space for code generation, which is already very difficult to navigate. Automatically tuned libraries like Atlas, FFTW and our Berkeley OSKI library represent an approach for getting high quality code generated for specific numerical kernels. Heterogeneous processors can fit into this model, as small code snippets written in assembly language can be incorporated into the search space. And at least two of the SciDAC efforts, PERI and CScADS, are working on generalizing these ideas to a new type of compiler which uses search during code generation. To me, the challenge represented by these processors is not the heterogeneity per se, but the difficulty of explicitly managing the memory systems, which may have separate memory spaces or alignment rules for some of the processors. The Cell processor and BG/L double hummer are good examples. If moving data within the heterogeneous processor is too expensive, these systems may not be effective. If they are fast but hard to use, the problem will be putting sufficient resources into the development of compilers, libraries, and applications software to take advantage of them.

HPCwire: The DARPA HPCS program heavily stresses productivity, along with performance. How can programming languages help productivity?

Yelick: The commercial world has experienced tremendous increases in productivity from language features such as strong typing, which catches errors early, garbage collection and the heavy use of libraries or components, which are made easier through simple interfaces that come from good language support. For example, if a user is managing memory allocation and deallocation, and keeping track of complex data types manually by passing type flags in the code, this significantly complicates the application code, but also make it more difficult to package components with clean interfaces that others are likely to understand easily and use.

HPCwire: Can good programming languages and other software get around bad machines?

Yelick: No. There is nothing software can do to get around bad machine design. Global address space languages like UPC, CAF, and Titanium are in some sense giving good hardware an advantage over bad by trying to expose features such as low overhead communication or global address space support. That said, one of the goals of the Berkeley UPC compiler is to make UPC an effective language for a larger class of machines and for less sophisticated programmers. We have advocated language extensions such as non-blocking bulk data reads and writes to allow programmers to obtain the best possible performance on clusters, and are also working on compiler technology to automatically optimize programs written in a fine-grained style. This could make programs written for a global address space machine like the Cray X1E run reasonably well on generic clusters--not as well as on the X1E, but reasonably well.

HPCwire: What are the limits of MPI's usefulness? What would it be like relying on MPI for petascale computing?

Yelick: MPI is likely to be a very popular and effective programming model on petascale machines. There are two issues, one related to performance and the other to ease of use. For performance, the problem is that the two-sided protocol in MPI, which involves message matching, and the requirement of message ordering all slow down data transfer. The fastest mechanism on a machine with minimal RDMA support is to write data directly from one processor into another processor's memory. Fast implementations of MPI do use this mechanism, but it requires some protocol overhead, since the remote address is not known to the sending processor. As we've shown in our UPC work, one-sided communication can be used in bisection-limited problems, like global FFTs, to improve communication overlap and reduce running time. At a petascale, bisection bandwidth is going to be expensive, and MPI may not give the best utilization of the network or the best management of memory due to the need for buffering. From an ease-of-use standpoint, I think the issue with MPI is that the community of petascale programmers, like terascale programmers today, will be small, because the barrier to entry for an application code is high. There are many computational scientists today who are not using parallel machines at all. This will have to change with the shift towards multi-core, but the question is whether they will adopt a scalable programming model.

HPCwire: Talk about the importance of partitioned global address space, or PGAS, programming languages.

Yelick: Aside from my answers to the previous question, PGAS languages offer a real advantage over OpenMP for shared memory platforms, because they give programmers the opportunity to express locality properties of the data structures. This makes the PGAS models an alternative to the hybrid MPI/OpenMP model for hierarchical machines, which has proven difficult to use.

But aside from the specifics on PGAS languages, I think they represent an important step in HPC programming models, because they've demonstrated that new languages are still a viable option, in spite of the backlash that occurred when HPF failed to take hold. The PGAS languages are popular within some government agencies and labs, including the work at AHPCRC on CFD codes in UPC. We have also learned some important lessons in the UPC process: interoperability with other programming models (in particular MPI) and ubiquity across platforms are essential to success. We have new methods for analyzing and quantifying productivity; and found that performance is still critical to swaying the most elite of HPC programmers.

HPCwire: What's the status of these languages today, including Berkeley UPC?

Yelick: UPC has an active community consortium that meets regularly to work on language design issues, maintain the language spec, and exchange implementation and application experience. There is a UPC compiler of some form for nearly every serial and parallel platform, including vendor compilers from Cray, HP, and IBM, and open source compilers from Intrepid, Inc., Michigan Tech and Berkeley Lab. The Berkeley compiler has optimized implementations using native communication layers for the Cray XT3, Quadrics, Myrinet, Altix, and the IBM SP platforms. Co-Array Fortran is being adopted into the Fortran spec, and in addition to the Cray CAF compiler, there is an open source effort led by John Mellor-Crummey at Rice. That compiler is designed for portability; it uses a source-to-source translation model like Berkeley UPC, and there are plans to do work on porting and releases in the near future. Titanium is still primarily a Berkeley effort, but it is used outside Berkeley and the compiler runs on many parallel and serial platforms. Berkeley UPC, Intrepid's gcc-upc, Titanium, and at least one instance of the Rice CAF compiler all use our open source communication layer called GASNet, which helps leverage the porting effort. These three PGAS languages will all be represented at the UPC booth (#342) at SC06. We will have compilers to install on your laptops, as well as posters and papers showing application experience and benchmark results.

HPCwire: Some people say that if there's a lot of pain involved, they won't switch to a new programming language. How can you motivate people to migrate to a more efficient new language?

Yelick: The key is that, because of interoperability, full applications do not need to be rewritten. Instead, individual components can be written in these languages as new algorithms are developed for the increasing machine scale. I am working with Parry Husbands and Esmond Ng, for example, on a fast sparse direct linear solver written in UPC. This may end up in an application without rewriting the rest of the code. And if the performance gains of new languages are significant, some people who care deeply about performance will switch. The harder argument is productivity, because while the community as a whole might save significant amounts of time and money in the long run by rewriting some code in new languages, this is difficult to quantify up front; and from the short term perspective of a 3-year or 5-year project, it is difficult to justify.

HPCwire: Where do you see MATLAB fitting into HPC, versus languages like UPC and CAF?

Yelick: MATLAB is very important, because the computational science and engineering communities in general (outside of HPC) are sold on the productivity advantage of MATLAB. They have voted with their feet by using MATLAB instead of languages like Fortran, C, C++ and Java. The problem is moving MATLAB into the large scale, both machine scale and software scale. The array statements in MATLAB make it a natural data parallel language, but more general forms of parallelism will be needed for large machines and irregular applications. There are several efforts to include parallelism in MATLAB by calling parallel libraries, extending the language, or performing compiler analysis on the code, and I think these will help to make parallel machines more accessible. On the other hand, I'm afraid that the difference between programming-in-the-small and programming-in-the-large (with separate modules, large application teams, complicated data structures and interfaces) are sometimes overlooked--languages that are very good at small programming tasks are not the best for large ones.

HPCwire: Will Fortran continue to be the fastest language? What about C and Java?

Yelick: This is an interesting question. Most vendor-supplied Fortran compilers share the backend, including optimization and code generation, with the C/C++ compilers. So in principle, the performance for the same program should be identical. There are still semantic differences between the languages, which will require the use of features like "restrict" in C/C++ to get the equivalent programs, and more of these may be needed in the C spec when it comes to multidimensional arrays. And programs that use all of the features of object-orientation and pointer-based data structures are unlikely to be as fast as their stripped-down counterparts. But the investment in Fortran compilers is not likely to be as high as in C/C++. Java is a different point on the spectrum: on the one hand the higher level of abstraction and need for automatic memory management add overhead, but the use of just-in-time compiler technology opens the door to optimizations that are not possible in a statically compiled environment.

HPCwire: Do you want to say anything about scaling algorithms for petascale computing?

Yelick: I think we need to rethink our algorithms to look for all possible sources of parallelism, rather than the single-level view that we have used recently. An upcoming SC06 paper with Shan, Strohmaier, Qiang, and Bailey is a case study in scaling and performance modeling, which reflects our ability to understand application performance on large machines. We look at a beam interaction application from accelerator modeling and develop a series of performance models to predict performance of this application code. Performance modeling, and therefore a simple understanding of performance, becomes increasingly difficult as the machines scale, as they become more hierarchical, and as network contention increases. All of these will be serious issues on petascale machines. The SC06 paper will be presented by Erich Strohmaier on Tuesday, Nov. 14, 4:30-5:00 in 22-23. We will also have copies of the paper and some of the authors will be around for questions at the LBNL booth (#1812) on the exhibit floor.

HPCwire: Is there anything important that we missed talking about?

Yelick: I think the introduction of parallelism into mainstream computing is both a challenge and opportunity for the HPC community. We must be able to handle the increase in parallelism along with everyone else, but if ever there was a time to innovate in parallel hardware, languages, and software, this is it. There are very likely to be new languages and programming models for multi-core programming, and the HPC community has the chance to take advantage of that software revolution by both influencing and using these innovations.


About NERSC and Berkeley Lab
The National Energy Research Scientific Computing Center (NERSC) is a U.S. Department of Energy Office of Science User Facility that serves as the primary high-performance computing center for scientific research sponsored by the Office of Science. Located at Lawrence Berkeley National Laboratory, the NERSC Center serves more than 7,000 scientists at national laboratories and universities researching a wide range of problems in combustion, climate modeling, fusion energy, materials science, physics, chemistry, computational biology, and other disciplines. Berkeley Lab is a DOE national laboratory located in Berkeley, California. It conducts unclassified scientific research and is managed by the University of California for the U.S. Department of Energy. »Learn more about computing sciences at Berkeley Lab.