Moving forward into the exascale era, NERSC users will place increased demands on NERSC computational facilities. Users will be facing increased complexity in the memory subsystem and node architecture. System designs and programming models will have to evolve to face these new challenges. NERSC staff are active in current initiatives addressing these problems through co-design efforts between DOE centers and various industry partners. Below are some of the programs in which we are currently involved.
The objective of the DesignForward program was to initiate partnerships between DOE centers and vendors to accelerate the research and development of critical technologies needed for exa-scale computing. The principal research areas of interest in the DesignForward program were in the general areas of system integration and interconnect technology. Broadly, the program was looking for proposals in the following areas: System Integration,including new node technologies, new programming models,… Read More »
The FastForward program complements the DesignForward program and focused on co-design efforts between DOE centers and vendors with the goal of improving processor, memory, storage and I/O technologies. Furthermore, these improvements should be aimed at maximizing energy efficiency and concurrency while increasing performance, productivity, and reliability. Further information and vendor documents can be found here and here. A follow on program to the original FastForward program,… Read More »
The goal of the Computer Architecture Laboratory (CAL) is engage in research and development into energy efficient and effective processor and memory architectures for DOE’s Exascale program. CAL coordinates hardware architecture R&D activities across the DOE. CAL is a joint NNSA/SC activity involving Sandia National Laboratories (CAL-Sandia) and Lawrence Berkeley National Laboratory (CAL-Berkeley), which will provide the following essential services to the DOE. Further information on… Read More »
Dynamic Frequency Scaling One means to lower the energy required to compute is to reduce the power usage on a node. One way to accomplish this is by lowering the frequency at which the CPU operates. However, reducing the clock speed increases the time to solution, creating a potential tradeoff. NERSC continues to examine how such methods impact its operations and its workload. Read a related paper: "Measurement and interpretation of micro benchmark and application energy use on the Cray… Read More »