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Intel Xeon Phi Webinar Series

July 2, 2015 by Richard Gerber

Intel, through a third-party trainer, is sponsoring a series of webinars focused on the Xeon Phi. You can register at



Wed, July 1 - "Hello world from Intel Xeon Phi coprocessors". Overview of architecture, preview of course topics. 
Thur, July 2 - "Offload programming for Intel coprocessors". Introduction to offload programming. 
Tue, July 7 - "Expressing Parallelism with Vectors". Vectorization reports, compiler hints, SIMD-enabled functions, array notation. 
Wed, July 8 - "Crash course on multi-threading with OpenMP“. Creating threads, parallel loops, synchronization. 
Thur, July 9 - "Optimization for Intel parallel architectures". Overview of optimization, motivational example. 
Tue, July 14 - "Optimization of vector arithmetics in Intel architectures". Data structures, alignment, regularizing vectorization pattern. 
Wed, July 15 - "Optimization of multi-threading in Intel architectures I". Efficient parallel reduction, expanding parallelism. 
Thur, July 16 - "Optimization of multi-threading in Intel architectures II". Load balancing, affinity control. 
Wed, July 29 - "Optimization of memory traffic in Intel parallel architectures". Loop tiling, cache-oblivious recursion. 
Thur, July 30 - "Practical usage of Intel Math Kernel Library with Intel Xeon Phi coprocessors". Usage modes, tuning, function support.