May 7, 2014 by Katie Antypas
NERSC's next supercomputer, Cori, will using the Xeon Phi processor architecture. In order to achieve high performance on Xeon Phi, users will need to find additional parallelism in application and take advantage of longer vector units. Intel is offering training sessions nationally, free to all NERSC users. Click on the link below to register.
May 5, 2014 by Francesca Verdier
In honor of its 40th Anniversary, NERSC is sponsoring a series of lectures describing the research behind four Nobel Prizes. The Laureates are also long-time users of NERSC’s supercomputing resources.
May 5, 2014 by Richard Gerber
Applications are now being accepted for the Broader Engagement (BE) Program at SC14, which will be held in New Orleans from November 16-21, 2014.
The BE Program is designed to diversify the pool of talent in high-performance computing (HPC) by introducing, engaging, and supporting students and professionals belonging to underrepresented minority groups. For more information, visit:http://sc14.supercomputing.org/engage/broader-engagement/
May 1, 2014 by Richard Gerber
Code vectorization will be important to performance on NERSC's Cori supercomputer when it arrives in 2016. You can start learning about vectorization now and experiment with the vector units on Edison. Read more about vectorization here.
April 29, 2014 by Francesca Verdier
NERSC and Cray Inc. announced today that they have signed a contract for NERSC's next supercomputer. The new Cray XC system will use Intel’s next-generation Intel® Xeon Phi™ processor –- code-named “Knights Landing” -- a self-hosted, manycore processor with on-package high bandwidth memory and delivers more than 3 teraFLOPS of double-precision peak performance per single socket node. Scheduled for delivery in mid-2016, the new system will deliver 10x the sustained computing capability of NERSC’s Hopper system.
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