The Green Flash platform provides a configurable, cycle-accurate, validated node design to understand the impact of node-architecture choices on application performance. Our research has built a foundation for hardware exploration that enables rapid synthesis of alternative CPU designs, methods for estimating peak power consumption, and benchmarking of full applications using validated hardware accelerated cycle accurate models of the resulting node design. Green Flash takes advantage of the RAMP FPGA-based hardware emulation platforms, which have emerged as a cost effective tool to prototype and run gate-level hardware implementations at near real-time speeds. In this project we will extend our cycle-accurate, node-level simulation tool to enable exploring application performance and practical advanced programming models, together with novel hardware support mechanisms that allow programmers to utilize massive on-chip concurrency, such as direct hardware support for PGAS on a chip. We will also extend our tool to support expanded instrumentation for performance introspection, more accurate power modeling, more scalable synthesis of manycore node designs, and targeted fault-injection to simulate transient errors in order to support the X-Stack resilience research.