As we enter the era of billion transistor chips, computer architects face significant challenges in effectively harnessing the large amount of computational potential available in modern CMOS technology. Given the challenges of heat density and resultant stall in clock frequency improvements, chip manufacturers are employing increased on-chip parallelism (multi-core, multi-thread) and increased architectural complexity (VLIW, deep cache hierarchies, stream prefetch) to improve performance. In this minisymposium, leaders in the field of computer architecture research will describe how to reign in architectural complexity and improve scientific productivity on future generations of parallel computing systems using innovative computer architectures.
Organizer:
John Shalf
Lawrence Berkeley National Laboratory / NERSC
David Patterson
University of California, Berkeley