NERSCPowering Scientific Discovery Since 1974

Harvey Wasserman

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Harvey J. Wasserman , Ph.D.
HPC Consultant
Phone: (510) 486-4750
Fax: (510) 486-4316
1 Cyclotron Road
Mail Stop 943-256
Berkeley, CA 94720

Biographical Sketch

Consultant Harvey Wasserman has been involved in workload characterization, benchmarking, and system evaluation at NERSC and at Los Alamos National Laboratory for over 30 years.  He helps run NERSC's program requirement reviews, participates in procurement-related activities, and also helps in tracking down and publicizing recent scientific discoveries made by NERSC users.

Conference Papers

M. J. Cordery, B. Austin, H. J. Wasserman, C. S. Daley, N. J. Wright, S. D. Hammond, D. Doerfler, "Analysis of Cray XC30 Performance using Trinity-NERSC-8 benchmarks and comparison with Cray XE6 and IBM BG/Q", SC'13, November 11, 2013,

Brian Austin, Matthew Cordery, Harvey Wasserman, Nicholas J. Wright, "Performance Measurements of the NERSC Cray Cascade System", 2013 Cray User Group Meeting, May 9, 2013,

Keith R. Jackson, Ramakrishnan, Muriki, Canon, Cholia, Shalf, J. Wasserman, Nicholas J. Wright, "Performance Analysis of High Performance Computing Applications on the Amazon Web Services Cloud", CloudCom, Bloomington, Indiana, January 1, 2010, 159-168,

Jonathan Carter, Yun (Helen) He, John Shalf, Hongzhang Shan, Erich Strohmaier, and Harvey Wasserman, "The Performance Effect of Multi-Core on Scientific Applications", Cray User Group 2007, May 2007, LBNL 62662,

The historical trend of increasing single CPU performance has given way to roadmap of increasing core count. The challenge of effectively utilizing these multi- core chips is just starting to be explored by vendors and application developers alike. In this study, we present some performance measurements of several complete scientific applications on single and dual core Cray XT3 and XT4 systems with a view to characterizing the effects of switching to multi-core chips. We consider effects within a node by using applications run at low concurrencies, and also effects on node- interconnect interaction using higher concurrency results. Finally, we construct a simple performance model based on the principle on-chip shared resource—memory bandwidth—and use this to predict the performance of the forthcoming quad-core system.

 

Book Chapters

Leonid Oliker, Jonathan Carter, V. Beckner, J. Bell, H. J. Wasserman, M. Adams, S. Ethier, and E. Schnetter, "Large-Scale Numerical Simulations on High-End Computational Platforms", Chapman & Hall/CRC Computational Science, edited by David H. Bailey, Robert F. Lucas, Samuel Williams, (Chapman & Hall/CRC Computational Science: November 23, 2010)

ISBN 9781439815694

Presentation/Talks

Harvey Wasserman, NERSC, New User Training: Introduction to NERSC, NUG 2014: NERSC Users' Group Meeting, February 3, 2014,

Richard A. Gerber, Harvey Wasserman, NERSC Requirements Reviews, February 12, 2013,

An update on the NERSC Requirements Reviews at NUG 2013. Richard Gerber and Harvey Wasserman, NERSC>

Harvey Wasserman, Simulation Science at NERSC, Cray Technical Workshop Japan, September 7, 2010,

Harvey Wasserman, Extreme Scale Data Intensive Computing at NERSC, Los Alamos Computer Science Symposium, Workshop on Performance Analysis of Extreme-Scale Systems and Applications, October 14, 2009,

John Shalf, Harvey Wasserman, Breakthrough Computing in Petascale Applications and Petascale System Examples at NERSC, HPC User Forum, April 10, 2009,

Harvey Wasserman, Future Scientific Computing Challenges at NERSC, University of Southampton, September 30, 2008,

Harvey Wasserman, Breakthrough Science at NERSC, Cray Technical Workshop, Europ, September 24, 2008,

J. Shalf, K. Antypas, H.J. Wasserman, Recent Workload Characterization Activities at NERSC, Santa Fe Workshop, January 1, 2008,

Jonathan Carter, Helen He*, John Shalf, Erich Strohmaier, Hongzhang Shan, and Harvey Wasserman, The Performance Effect of Multi-Core on Scientific Applications, Cray User Group 2007, May 2007,

Reports

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Fusion Energy Sciences: Target 2017", May 1, 2014,

Richard Gerber and Harvey Wasserman, eds., "Large Scale Computing and Storage Requirements for High Energy Physics - Target 2017", November 8, 2013,

Richard Gerber, Harvey Wasserman, "High Performance Computing and Storage Requirements for Biological and Environmental Research Target 2017", June 6, 2013, LBNL LBNL-6256E,

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Nuclear Physics", Workshop, March 26, 2012, LBNL LBNL-5355E,

Report of the user requirements workshop for lattice gauge theory and nuclear physics computation at NERSC that took place May 26, 2011

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Advanced Computational Science Research", Workshop, January 2012, LBNL LBNL-5249E,

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Fusion Energy Sciences", Workshop, December 2011,

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Basic Energy Sciences", Workshop, June 10, 2011, LBNL LBNL-4809E,

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for High Energy Physics", Workshop, November 15, 2010,

Richard A. Gerber, Harvey J. Wasserman, "Large Scale Computing and Storage Requirements for Biological and Environmental Research", Workshop, October 19, 2009, LBNL LBNL-2710E,

Antypas, K., Shalf, J., Wasserman, H., "NERSC‐6 Workload Analysis and Benchmark Selection Process", LBNL Technical Report, August 13, 2008, LBNL 1014E,

Science drivers for NERSC-6

K. Antypas, J. Shalf, H. Wasserman, "NERSC-6 Workload Analysis and Benchmark Selection Process", January 1, 2008,

J. Levesque, J. Larkin, M. Foster, J. Glenski, G. Geissler, S. Whalen, B. Waldecker, J. Carter, D. Skinner, H. He, H. Wasserman, J. Shalf, H. Shan, "Understanding and mitigating multicore performance issues on the AMD opteron architecture", March 1, 2007, LBNL 62500,

Over the past 15 years, microprocessor performance has doubled approximately every 18 months through increased clock rates and processing efficiency. In the past few years, clock frequency growth has stalled, and microprocessor manufacturers such as AMD have moved towards doubling the number of cores every 18 months in order to maintain historical growth rates in chip performance. This document investigates the ramifications of multicore processor technology on the new Cray XT4systems based on AMD processor technology. We begin by walking through the AMD single-core and dual-core and upcoming quad-core processor architectures. This is followed by a discussion of methods for collecting performance counter data to understand code performance on the Cray XT3and XT4systems. We then use the performance counter data to analyze the impact of multicore processors on the performance of microbenchmarks such as STREAM, application kernels such as the NAS Parallel Benchmarks, and full application codes that comprise the NERSC-5 SSP benchmark suite. We explore compiler options and software optimization techniques that can mitigate the memory bandwidth contention that can reduce computing efficiency on multicore processors. The last section provides a case study of applying the dual-core optimizations to the NAS Parallel Benchmarks to dramatically improve their performance.1